Leon/grlib design and Configuration Guide

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An example instantiation of AT_AHB_SLV can be found in verification/at/at_tb.vhd. At the top of 

the  file  the  libraries  mentioned  above  is  included.  The  signals  used  to  make  accesses  to AT_AH-

B_SLV’s debug interface are created with:

signal dbgi  : at_slv_dbg_in_type;

signal dbgo  : at_slv_dbg_out_type;

An example instantiation of AT_AHB_SLV looks like:

ahbslv0 : at_ahb_slv

    generic map (

      hindex        => 0,

      -- Bank 0 configuration;

      bank0addr => 16#000#,

      bank0mask => 16#FFF#,

      bank0type => AT_AHBSLV_MEM,

      bank0cache => 1,

      bank0prefetch => 1,

      bank0ws => 1,

      bank0rws => AT_AHBSLV_FIXED_WS,

      bank0dataload => 0,

      bank0datafile => "none")

    port map (

      rstn => rstn, clk => clk, 

      ahbsi => ahbsi, ahbso => ahbso(0),

      dbgi => dbgi, dbgo => dbgo);

After the rstn signal has gone high the core will be ready to handle incoming AMBA accesses. If no 

file is used to initialize the memory, all memory position will contain ‘U’.

7.3.3  Controlling AT_AHB_SLV

When  the  slave  has  left  system  reset  (rstn  input  is  high),  the  procedures  defined  in  grlib.at_ah-

b_slv_pkg (lib/grlib/atf/at_ahb_slv_pkg.vhd) can be used to control the slave’s behavior and to access 

the slave’s internal memory. 

Accesses to the slave’s internal memory are made via the ahbslv_read(..) and ahbslv_write(..) proce-

dures. These procedures have the following interface:

  -- Subprogram: ahbslv_write

  -- Description: Write data to slave memory. The input address is masked and

  --              only the valid bits are used. This means that the full AMBA

  --              address can be used and the caller does not have to subtract

  --              the bank start address.

  procedure ahbslv_write (

    constant address : in  std_logic_vector(ADDR_R);

    constant data    : in  std_logic_vector;

    constant bank    : in  integer;

    signal   dbgi    : out at_slv_dbg_in_type;

    signal   dbgo    : in  at_slv_dbg_out_type);

  -- Subprogram: ahbslv_read

  -- Description: Read data from slave memory. The input address is masked and

  --              only the valid bits are used. This means that the full AMBA

  --              address can be used and the caller does not have to subtract

  --              the bank start address.

  procedure ahbslv_read (

    constant address : in  std_logic_vector(ADDR_R);

    variable data    : out std_logic_vector;

    constant bank    : in  integer;

    signal   dbgi    : out at_slv_dbg_in_type;

    signal   dbgo    : in  at_slv_dbg_out_type);

These  functions  are  useful  quickly  initializing  memory  or  to  check  the  result  of AMBA  accesses 

made to the slave without generating traffic on the AMBA AHB bus. The width of the vector assigned 

to the data parameter determines the size of the access. The width of the address vector input must be 

32 bits (31 downto 0).

A common use of AT_AHB_SLV is to specify special responses in order to test the behavior of AHB

 

masters in the system. Custom responses can be inserted with the ahbslv_response(..) procedure. This 

procedure name is overloaded and variants with a different number of parameters exist. The most ver-

satile ahbslv_response(..) procedure is:

  procedure ahbslv_response (

    constant address_start  : in  std_logic_vector(ADDR_R);

    constant address_stop   : in  std_logic_vector(ADDR_R);

    constant bank           : in  integer;

    constant response       : in  std_logic_vector(1 downto 0);

    constant data           : in  std_logic_vector;

    constant master         : in  integer range 0 to NAHBMST-1;

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    constant anymst         : in  boolean;

    variable id             : out integer;

    signal   dbgi           : out at_slv_dbg_in_type;

    signal   dbgo           : in  at_slv_dbg_out_type;

    constant ws             : in  integer := 0;

    constant repeat         : in  integer := 1;

    constant count          : in  integer := 1;

    constant splitcnt       : in  integer := 5;

    constant mem_access     : in  boolean := false;

    constant read_response  : in  boolean := true;

    constant write_response : in  boolean := true;

    constant lock           : in  boolean := false;

    constant delay          : in  integer := 0;

    constant hprot          : in  std_logic_vector(3 downto 0);

    constant anyhprot       : in  boolean);

The parameters are documented in the grlib.at_ahb_slv_pkg package. Note that several parameters 

have default values,  this means that they  do not have to  be  assigned  when  using the  procedure. A

 

selection of available AT_AHB_SLV procedures are listed in table 12. All procedures are further doc-

umented in the grlib.at_ahb_slv_pkg package located at lib/grlib/atf/at_ahb_slv_pkg.vhd.

TABLE 12. Selection of AT_AHB_SLV procedures

Procedure name

Description

ahbslv_response

Inserts a customized response into the slaves response queue. If two 

responses are inserted for the same address (range), the first response to be 

inserted will be the first given. Several overloaded versions exist giving the 

ability to, for instance, only replying to accesses from a specific master that 

have a specific HPROT value. When a response is inserted, an unique iden-

tifier for that response is returned.

ahbslv_response_status

Used to determine if a response with a specified identifier is in the slave’s 

response queue.

ahbslv_response_remove

Removes a response with a specified identifier from the slave’s response 

queue.

ahbslv_response_clear

Removes all queue responses in the slave or only for a specified bank.

ahbslv_response_unlock

A response inserted with ahbslv_response(..) can be “locked” which means 

that it will be valid for an unlimited number of accesses. This procedure can 

be used to “unlock” the response, removing it from the slave.

ahbslv_waitforaccess

This procedure will block until an access has been made to a specified 

memory address.

ahbslv_waitforcomplete

This procedure will block until a queued response has been triggered and 

removed from the slave’s response queue.

ahbslv_setconfig

Changes the default behavior of AHB slave model. Can be used to config-

ure wait states, random wait states, random RETRY and SPLIT responses, 

etc.

ahbslv_getconfig

Reads the current default behavior of the slave.

ahbslv_enable_split

Enables SPLIT responses with a specified probability.

ahbslv_disable_split

Disables SPLIT responses.

ahbslv_enable_retry

Enables RETRY responses with a specified probability.

ahbslv_disable_retry

Disables RETRY responses.

ahbslv_set_ws

Sets the default number of wait states to be inserted by the slave.

ahbslv_get_ws

Gets the default number of wait states inserted by the slave.

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7.4

AT AHB Controller

7.4.1  Description

The AT AHB  Controller  (AT_AHB_CTRL)  is  an  non-synthesizable AHB  arbiter/controller.  Com-

pared to the standard GRLIB AHBCTRL core, AT_AHB_CTRL supports early burst termination and 

forced re-arbitration

7.4.2  Usage

In order to instantiate the controller, the following libraries should be included:

library ieee;

use ieee.std_logic_1164.all;

library grlib;

use grlib.amba.all;

use grlib.at_pkg.all;

The component for AT_AHB_CTRL has the following interface:

   component at_ahb_ctrl is

     generic (

       defmast     : integer := 0;

-- default master

       split       : integer := 0;

-- split support

       rrobin      : integer := 0;

-- round-robin arbitration

       timeout     : integer range 0 to 255 := 0;  -- HREADY timeout

       ioaddr      : ahb_addr_type := 16#fff#;  -- I/O area MSB address

       iomask      : ahb_addr_type := 16#fff#;  -- I/O area address mask

       cfgaddr     : ahb_addr_type := 16#ff0#;  -- config area MSB address

       cfgmask     : ahb_addr_type := 16#ff0#;  -- config area address mask

       nahbm       : integer range 1 to NAHBMST := NAHBMST; -- number of masters

       nahbs       : integer range 1 to NAHBSLV := NAHBSLV; -- number of slaves

       ioen        : integer range 0 to 15 := 1;    -- enable I/O area

       disirq      : integer range 0 to 1 := 0;     -- disable interrupt routing

       fixbrst     : integer range 0 to 1 := 0;     -- support fix-length bursts

       debug       : integer range 0 to 2 := 2;     -- report cores to console

       fpnpen      : integer range 0 to 1 := 0; -- full PnP configuration decoding

       icheck      : integer range 0 to 1 := 1;

       devid       : integer := 0;

     -- unique device ID

       enbusmon    : integer range 0 to 1 := 0; --enable bus monitor

       assertwarn  : integer range 0 to 1 := 0; --enable assertions for warnings 

       asserterr   : integer range 0 to 1 := 0; --enable assertions for errors

       hmstdisable : integer := 0; --disable master checks           

       hslvdisable : integer := 0; --disable slave checks

       arbdisable  : integer := 0; --disable arbiter checks

       mprio       : integer := 0; --master with highest priority

       mcheck      : integer := 1; --check memory map for intersects

       enebterm    : integer := 0; --enable early burst termination

       ebprob      : integer := 10; --probability setting for of early bursttermination

       ccheck      : integer range 0 to 1 := 1;  --perform sanity checks on pnp config

       acdm        : integer := 0  --AMBA compliant data muxing (for hsize > word) 

       );

     port (

       rst     : in  std_ulogic;

       clk     : in  std_ulogic;

       msti    : out ahb_mst_in_type;

       msto    : in  ahb_mst_out_vector;

       slvi    : out ahb_slv_in_type;

       slvo    : in  ahb_slv_out_vector;

       testen  : in  std_ulogic := '0';

       testrst : in  std_ulogic := '1';

       scanen  : in  std_ulogic := '0';

       testoen : in  std_ulogic := '1';

       doarb   : in  std_ulogic := '0'

     );

   end component;

Most of the core’s VHDL generics are the same as for the AHBCTRL core. Two generics have been 

added: enebterm and ebprob. When enebterm is set to a non-zero value the core may automatically 

terminate burst accesses early. The normal GRLIB arbiter, AHBCTRL, does not interrupt a burst by 

removing grant  from a master. With enebterm /= 0 and ebprob  set  to  10 the probability of a burst 

being interrupted by AT_AHB_CTRL is about 0.10 in each cycle.

Bursts may also be terminated early by assertion of the doarb input signal. When doarb is asserted, 

the AHB arbiter will perform arbitration.

Use of AT_AHB_CTRL is primarily recommended when a core will be used in non-GRLIB systems. 

The GRLIB arbiter will never interrupt a burst access and it is not a strict requirement that a core can 

handle terminated bursts for the core to function in GRLIB.

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8

Support

Cobham Gaisler AB provides support via [e-mail] for customers with support contracts. 

Limited free support is also provided by Cobham Gaisler engineers on the leon_sparc Yahoo! group 

found at http://tech.groups.yahoo.com/group/leon_sparc/. This group also has a searchable archive.

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Copyright © 2018 Cobham Gaisler AB

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Document Outline

• 1 Introduction
  • 1.1 Overview
  • 1.2 Other Resources
  • 1.3 Licensing
• 2 System Design Guidelines
  • 2.1 Introduction
  • 2.2 Minimal System
  • 2.3 Memory Map
    • 2.3.1 Overview
    • 2.3.2 Typical LEON/GRLIB Memory Map
    • 2.3.3 Memory Map in Systems That Need 2 GiB Memory Area
    • 2.3.4 AHB I/O Area and GRLIB Plug&Play Areas
  • 2.4 Interrupt Assignments
    • 2.4.1 Overview
    • 2.4.2 Linux 2.6 and later
    • 2.4.3 RTEMS
    • 2.4.4 VxWorks
  • 2.5 Device Specific Identification
• 3 LEON design information
  • 3.1 Introduction
  • 3.2 General Recommendations
    • 3.2.1 Data Cache Snooping
    • 3.2.2 V7 and FPU
    • 3.2.3 MMU and Supervisor Tag bit
  • 3.3 LEON Example Configurations
    • 3.3.1 Overview
    • 3.3.2 Minimal LEON Configuration
    • 3.3.3 General Purpose LEON Configuration
    • 3.3.4 High Performance LEON Configuration
    • 3.3.5 Configuration Settings For Existing LEON Devices
  • 3.4 LEON subsystem (gaisler.subsys.leon_dsu_stat_base)
• 4 Multiple Buses, Clock Domains and Clock Gating
  • 4.1 Introduction
  • 4.2 Creating Multi-Bus Systems
    • 4.2.1 Overview
    • 4.2.2 GRLIB Facilities
    • 4.2.3 GRLIB AMBA Plug&Play in Multi-Bus Systems
    • 4.2.4 Buses in Different Clock Domains
    • 4.2.5 Single AHB Bus Example
    • 4.2.6 Multi-Bus System Example
  • 4.3 LEON3 Double-Clocking
    • 4.3.1 Overview
    • 4.3.2 LEON3-CLK2X Template Design
    • 4.3.3 Clocking
    • 4.3.4 Multicycle Paths
    • 4.3.5 Dynamic Clock Switching
    • 4.3.6 Configuration
  • 4.4 Clock gating
    • 4.4.1 Overview
    • 4.4.2 LEON clock gating
• 5 Debug communication links
  • 5.1 Overview
  • 5.2 Available debug link controllers
• 6 Core specific design recommendations
  • 6.1 Overview
  • 6.2 AHB/AHB Bridges (AHB2AHB/AHBBRIDGE/GRIOMMU)
  • 6.3 SVGA Controller (SVGACTRL)
• 7 GRLIB AMBA Test Framework
  • 7.1 Overview
  • 7.2 AT AHB Master
    • 7.2.1 Description
    • 7.2.2 Initialization and Instantiation
    • 7.2.3 Simple Accesses
  • 7.3 AT AHB Slave
    • 7.3.1 Description
    • 7.3.2 Initialization and Instantiation
    • 7.3.3 Controlling AT_AHB_SLV
  • 7.4 AT AHB Controller
    • 7.4.1 Description
    • 7.4.2 Usage
• 8 Support