Leon/grlib design and Configuration Guide

GUIDE, Apr 2018, Version 2018.1

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LEON/GRLIB Guide

3.3.3  General Purpose LEON Configuration

This  LEON  configuration  is  aimed  for  general  purpose  processing  balancing  performance  against 

area and power requirements.

TABLE 7. General purpose LEON processor configuration

VHDL 

generic

Recommended 

value

Description

dsu

1

Include support for the LEON Debug Support Unit (DSU)

fpu

-

Include floating-point unit based on application requirements. A 

floating-point unit is highly recommended for most systems. 

LEON processors can primarily interface the GRFPU or GRFPU-

lite floating point unit. The GRFPU is a high-performance pipe-

lined FPU with high area requirements. GRFPU-lite provides a 

balanced option with high acceleration of floating-point computa-

tions combined with lower area requirements compared to 

GRFPU.

v8

2

Include support for SPARC V8 MUL/DIV instructions using a 5-

cycle multiplier. Note that if the target technology has multiplier 

blocks a single-cycle multiplier (v8 generic set to 1) may provide 

lower area and higher performance.

mac

0

Do not include support for SPARC V8e SMAC/UMAC instruc-

tions.

nwp

2

Include two hardware watchpoints

icen / dcen

1

Include processor caches.

isets / dsets

2

Implement instruction and data caches with two ways

irepl / drepl

2

Random replacement policy for both instruction and data cache, or 

possibly LRU replacement (irepl/drepl set to 0).

isetsize / 



dsetsize

-

The size of the caches does not significantly affect the required 

logic. Choose cache size according to application requirements and 

amount of RAM available on target device.

dnsoop

6

Enable snooping with extra physical tags (see section 3.2.1)

mmuen

2

Enable memory management unit (MMU)

itlbnum / 



dtlbnum

8

Use eight entries each for the instruction and data MMU transla-

tion look-a-side buffers

tlb_type

2

Use separate translation look-a-side buffers (TLB) with fast write 

for data and instruction.

tlb_rep

0

Use LRU TLB replacement

lddel

1

Use 1-cycle load delay

tbuf

4

Use 4 KiB instruction trace buffer.

pwd

2

Timing efficient power-down implementation.

smp

0

Disable SMP support. If the processor core should be used in an 

SMP configuration then see the GRIP documentation on how to set 

the SMP generic.

bp

1

Enable branch prediction

3.3.4  High Performance LEON Configuration

This LEON configuration is aimed at high performance processing where the needs for computational 

speed outweighs area and power requirements.

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GUIDE, Apr 2018, Version 2018.1

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LEON/GRLIB Guide

In order to reduce the effects of memory latency, a Level-2 cache is recommended for high-perfor-

mance systems. This is of particular interest in multiprocessor systems.

TABLE 8. High-performance LEON processor configuration

VHDL 

generic

Recommended 

value

Description

dsu

1

Include support for the LEON Debug Support Unit (DSU)

fpu

1 - 7

Use GRFPU floating-point unit. Select (FP) multiplier depending 

on target technology. For FPGA this would typically be inferred 

(1) or technology specific (4). For ASIC DesignWare multiplier 

(2) or Module Generator (3).

v8

16#32#

Include support for SPARC V8 MUL/DIV instructions using a 

32x32 pipelined multiplier. Note that if the target technology has 

multiplier blocks a single-cycle multiplier (v8 generic set to 1) 

may provide lower area and higher performance.

mac

0

Do not include support for SPARC V8e SMAC/UMAC instruc-

tions

nwp

4

Include support for four hardware watchpoints

icen / dcen

1

Include processor caches.

isets / dsets

2

Implement instruction and data caches with two ways

irepl / drepl

0

Least-Recently-Used replacement policy for instruction and data 

caches.

isetsize / 



dsetsize

-

The size of the caches does not significantly affect the required 

logic. Choose cache size according to application requirements and 

amount of RAM available on target device.

dnsoop

6

Enable snooping with extra physical tags (see section 3.2.1)

mmuen

2

Enable memory management unit (MMU)

itlbnum / 



dtlbnum

16

Use sixteen entries each for the instruction and data MMU transla-

tion look-a-side buffers

tlb_type

2

Use separate translation look-a-side buffers (TLB) with fast write 

for data and instruction.

tlb_rep

0

Use LRU TLB replacement

lddel

1

Use 1-cycle load delay

tbuf

4

Use 4 KiB instruction trace buffer.

pwd

2

Timing efficient power-down implementation.

smp

> 0

Enable SMP support. If the processor core should be used in an 

SMP configuration then see the GRIP documentation on how to set 

the SMP generic. Note that several processor entities must be 

instantiated. This configuration option only enables support for 

SMP, it does not instantiate several processor cores.

bp

1

Enable branch prediction

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