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Debug communication links ................................................................................. 22
5.1
Overview ........................................................................................................................... 22
5.2
Available debug link controllers........................................................................................ 22
6
Core specific design recommendations ................................................................ 23
6.1
Overview ........................................................................................................................... 23
6.2
AHB/AHB Bridges (AHB2AHB/AHBBRIDGE/GRIOMMU)........................................ 23
6.3
SVGA Controller (SVGACTRL) ...................................................................................... 23
7
GRLIB AMBA Test Framework ........................................................................... 24
7.1
Overview ........................................................................................................................... 24
7.2
AT AHB Master................................................................................................................. 24
7.2.1
Description.......................................................................................................... 24
7.2.2
Initialization and Instantiation ............................................................................ 24
7.2.3
Simple Accesses.................................................................................................. 25
7.3
AT AHB Slave ................................................................................................................... 26
7.3.1
Description.......................................................................................................... 26
7.3.2
Initialization and Instantiation ............................................................................ 26
7.3.3
Controlling AT_AHB_SLV................................................................................. 28
7.4
AT AHB Controller............................................................................................................ 30
7.4.1
Description.......................................................................................................... 30
7.4.2
Usage................................................................................................................... 30
8
Support.................................................................................................................. 31
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LEON/GRLIB Guide
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Introduction
1.1
Overview
The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SoC)
development. The IP cores are centered around a common on-chip bus, and use a coherent method for
simulation and synthesis. The library is vendor independent, with support for different CAD tools and
target technologies. A unique plug&play method is used to configure and connect the IP cores with-
out the need to modify any global resources.
The LEON3 and LEON4 processors are synthesisable VHDL models of 32-bit processor compliant
with the SPARC V8 architecture. The models are highly configurable and particularly suitable for
SoC designs. Both LEON3 and LEON4 are distributed as integrated parts of the GRLIB IP Library.
This configuration and development guide is intended to aid designers when developing systems
based on LEON/GRLIB. The guide complements the GRLIB IP Library User’s Manual and the
GRLIB IP Core User’s Manual. While the IP Library user’s manual is suited for RTL designs and the
IP Core user’s manual is suited for instantiation and usage of specific cores, this guide aims to help
designers make decisions in the specification stage.
1.2
Other Resources
There are several documents that together describe the GRLIB IP Library and Cobham Gaisler’s IP
cores:
•
GRLIB IP Library User’s Manual (grlib.pdf) - Main GRLIB document that describes the library
infrastructure, organization, tool support and on-chip bus.
•
GRLIB IP Core User’s Manual (grip.pdf) - Describes specific IP cores provided with the GRLIB
IP library. Also specifies which cores that are included in each type of GRLIB distribution.
•
GRLIB-FT User’s Manual (grlib-ft.pdf) - Describes the FT and FT-FPGA versions of the GRLIB
IP library. The document is an addendum to the GRLIB IP Library User’s Manual. This docu-
ment is only available in the FT and FT-FPGA distributions of GRLIB.
•
GRLIB FT-FPGA Xilinx Add-on User’s Manual (grlib-ft-fpga-xilinx.pdf) - Describes function-
ality of the Virtex5-QV and Xilinx TMRTool add-on package to the FT-FPGA version of the
GRLIP IP library. The document should be read as an addendum to the ‘GRLIB IP Library
User’s Manual’ and to the GRLIB FT-FPGA User’s Manual. This document is only available as
part of the add-on package for FT-FPGA.
1.3
Licensing
Some of the cores mentioned in this document (such as LEON4 and the AHB bridges) are only avail-
able in the commercial versions of GRLIB.