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Ch340 Datasheet (I) 1 usb to Serial Port Chip ch340 DTR and multi-mode MCU downloadCH340DS1 (1)5.3. DTR and multi-mode MCU download
For CH340X, 6# Pin defaults to TNOW, weak pull-up during power-on or reset, output TNOW during
normal operation used for half-duplex transceiver switchover. By connecting an external resistor with 6# pin,
TNOW can be switch to DTR#, the two options are as follows:
①
If the 4.7K
Ω
pull-down resistor is connected to GND with the 6# pin, it will enter the open source DTR
enhanced mode, and the 6# pin will automatically switch to the open source driven DTR# pin , which is
used to connect the boot mode pin of MCU. The default DTR # is not output and is kept low by the
external resistor, but the DTR# pin can be set to output high level or not output by the application
program, which is used for multi-mode MCU download with DTR# default low level.
②
If a 4.7K
Ω
resistor is connected between the 6# pin and the 5# pin, it will enter the push-pull DTR
enhanced mode, and the 6# pin will automatically switch to the push-pull driven DTR# for connecting to
the control pin of the MCU. The application program sets the DTR# pin to output high or low level for
multi-mode MCU download with DTR# default high level.
For CH340C with batch number begin with 4 and last 3-digit greater than B40, 8# pin defaults to OUT#,
weak pull-up during power-on or reset, output MODEM OUT# during normal operation. If 8# pin is
connected to a 4.7K
Ω
pull-down resistor, into open source DTR enhanced mode, 8# pin switches to the
open source driver's second DTR# automatically, connects BOOT mode of MCU, By default the second
DTR# is not output, kept low by external resistor, but DTR# pin can be set by the application to output high
or no, for DTR# default low level Multi-mode MCU download. In addition, 13# pin original DTR# is used
for DTR# default high level Multi-mode MCU download.
5.4. UART features
CH340 has integrated separate transmit-receive buffer and supports simplex, half-duplex and full duplex
UART communication. Serial data contains one low-level start bit, 5, 6, 7 or 8 data bits and 1 or 2 high-level
stop bits, supports odd/even/mark/space/none parity CH340 supports common baud rate: 50, 75, 100, 110,
134.5, 150, 300, 600, 900, 1200, 1800, 2400, 3600, 4800, 9600, 14400, 19200, 28800, 33600, 38400, 56000,
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