B e-electronics and communication engineering

UNIT I BOOLEAN ALGEBRA 9

Number systems-weighted and nonweighted codes- Logic gates-Boolean postulates and laws –De-Morgan’s Theorem- Principle of Duality- Boolean expression -Minimization of Boolean expressions – Sum of Products (SOP) –Product of Sums (POS)- Conversion between canonical forms -Karnaugh map Minimization – Quine Mcclusky Method. NAND/NOR implementations –Multi level gate implementations- Multi output gate implementations.

UNIT II COMBINATIONAL AND SEQUENTIAL CIRCUITS 9

Design procedure – Adders - Subtractors – Serial adder/Subtractor - Parallel adder/ Subtractor- Carry look ahead adder- BCD adder- Magnitude Comparator- Multiplexer/ Demultiplexer- encoder / decoder – parity checker – code converters. Implementation of combinational logic using MUX, ROM, PAL and PLA.

Flip flops : SR, JK, T, D and Master slave – Characteristic table and equation –Excitation table – Edge/Level/Pulse Triggering –Realization of one flip flop using other flip flops –Asynchronous Ripple counters – Synchronous Modulo-n Counters, Special counters, Shift registers.
UNIT III DESIGN OF SEQUENTIAL CIRCUIT 9

SYNCHRONOUS CIRCUITS: Moore and Mealy machine-Design of Synchronous counters: state diagram- State table –State minimization –State assignment- Excitation table and maps-Circuit implementation.

ASYNCHRONOUS CIRCUITS: Design of fundamental mode and pulse mode circuits – primitive flow table – Minimization of primitive state table –state assignment – Excitation table – Excitation map- Cycles, Races and Hazards–Hazard free design. Design issues like metastability, clock skew and timing considerations

UNIT IV MEMORY DEVICES 9

TTL and CMOS Logic and their characteristics - Classification of memories –RAM organization – Read and write operations – Memory decoding – Memory expansion – SRAM Cell- DRAM cell –ROM organization - PROM –EPROM –EEPROM–Programmable Logic Devices –PLA, PAL, FPGA.
UNIT V INTRODUCTION TO VHDL 9

Complete VLSI design flow, Behavioral, Data flow, and Structural Modeling. Functions, Procedures, attribute, Test bench, Packages and configurations.

VHDL implementation of Adder, comparator, MUX, Decoder, parity checker , flip flops, Counters, Shift register.
TUTORIAL 15

TOTAL 60


TEXT BOOKS

1. 
   M. Morris Mano, Digital Design, 3.ed., Prentice Hall of India Pvt. Ltd., New Delhi, 2003/Pearson Education (Singapore) Pvt. Ltd., New Delhi, 2003.
   
2. 
   Charles H.Roth. “Fundamentals of Logic Design”, Thomson Publication Company,2003.
   
3. 
   VHDL Primer, J. Bhaskar , Pearson / PHI, NewDelhi, 2003.
   

REFERENCE BOOKS

1. 
   S. Salivahanan and S. Arivazhagan, Digital Circuits and Design, 2^nd ed., Vikas Publishing House Pvt. Ltd, New Delhi, 2004.
   
2. 
   Digital Systems Design Using VHDL, - Thomson Learning - Charles H. Roth. Jr: Inc, 2002.
   
3. 
   Donald P.Leach and Albert Paul Malvino, Digital Principles and Applications, 5 ed., Tata McGraw Hill Publishing Company Limited, New Delhi, 2003.
   
4. 
   R.P.Jain, Modern Digital Electronics, 3 ed., Tata McGraw–Hill publishing company limited, New Delhi, 2003.
   
5. 
   Thomas L. Floyd, Digital Fundamentals, Pearson Education, Inc, New Delhi, 2003.
   
6. 
   Donald D.Givone, Digital Principles and Design, Tata Mc-Graw-Hill Publishing Company limited, New Delhi, 2003.
   

11UEC3003 NETWORK ANALYSIS AND SYNTHESIS 3 1 0 4
OBJECTIVES

At the end of the course the student should be able

• 
  To know about the analysis of networks in s domain.
  
• 
  To know about the various elements of network synthesis.
  
• 
  To design active and passive filters.
  

UNIT I ANALYSIS OF NETWORKS IN 'S' DOMAIN 9

Network Elements, Transient and Sinusoidal Steady State Analysis, Network analysis using Laplace transformation, Network functions, Two port networks: Parameters and transfer function, Interconnection of two ports.

UNIT II METHODS FOR COMPUTER AIDED NETWORK ANALYSIS 9

State variable method, Analytic and numerical solutions, Graph theoretic analysis for large scale networks, Formulation and solution of network graph of simple networks, State space representation, Analysis using PSPICE.

UNIT III ELEMENTS OF NETWORK SYNTHESIS 9

Network reliability, Hurwitz Polynomials, Positive real functions, Properties of RC, RL and LC networks, Foster and Couer forms of realization, Transmission zeroes, Synthesis of transfer functions.

UNIT IV PASSIVE FILTER DESIGN 9

Butter worth and Chebyshev approximations, Normalized specifications, Frequency transformations, Frequency and impedance denormalisation, Types of frequency selective filters, Linear phase filters.

UNIT V ACTIVE FILTER DESIGN 9

Controlled sources, Op-amp as a controlled source, Sallen and key structure, Single amplifier Low Pass, High Pass, Band Pass and Band Reject filters, Principle of design, Sensitivity.

TUTORIAL 15

TOTAL: 60

TEXT BOOKS

1. 
   Someshwar C. Gupta, Jon W. Bayless, Behrouz Peikari, “Circuit Analysis - with computer applications to problem solving”, Wiley-Eastern Ltd., 1991.
   
2. 
   Louis Weinberg, “Network Analysis and Synthesis”, McGraw Hill Book Company Inc., 1962.
   
3. 
   Vasudev K. Aartre, “Network Theory and Filter Design”, Wiley-Eastern Ltd., Second Edition, 1993.
   
4. 
   D. Roy Choudhary, “Networks and Systems” Wiley Eastern Ltd.
   
5. 
   Donald E. Scott: “An Introduction to Circuit analysis: A System Approach” McGraw Hill
   

REFERENCE BOOKS

1. 
   Franklin F. Kuo, “Network Analysis and Synthesis”, John Wiley.
   
2. 
   Vanvalkenburg, “Network Analysis”, Prentice Hall of India Pvt. Ltd., New Delhi, 1994.
   
3. 
   Lawrence P. Huelsman, " Active and Passive Analog Filter Design”, McGraw Hill, 1993.
   

11UEE3012 ELECTRICAL MACHINES 3 0 0 3

Objectives