Program Control Instructions a course in Microprocessor



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Program Control Instructions

  • A Course in Microprocessor

  • Electrical Engineering Dept.

  • University of Indonesia


The Jump Group

  • Jump (JMP) allows the programmer to skip sections of a program and branch to any part of the memory for the next instruction

  • A Conditional Jump allows the programmer to make decisions based upon numerical test

  • Unconditional Jump (fig.6.1)

    • Short Jump
      • a 2-byte instruction that allows jumps or branches to memory locations within +127 and -128 bytes from the address following the jump
      • is called relative jump


The Jump Group (cont’d)

      • the jump address is not stored with the opcode but a distance or displacement follows the opcode
      • See fig.6.2 and study example 6.1
    • Near Jump
      • It passes control to an instruction in the current code segment located within 32K bytes from the near jump
      • The near jump is relocatable known as relative jump
      • See fig.6.3 and study example 6.2
    • Far Jump
      • It obtains new segment and offset address to accomplish the jump (fig.6.4 and example 6.3)


The Jump Group (cont’d)

    • Jumps with Register Operands
      • known as indirect jump
      • the address of the jump is in the register specified by the jump instruction (i.e., the contents of the register are transferred directly into the instruction pointer)
      • Study example 6.4
    • Indirect Jump Using an Index
      • It uses the [] form of addressing to directly access the jump table
      • The JMP Table [SI] instruction (example 6.5) points to a jump address stored at the code segment offset loction addressed by SI


The Jump Group (cont’d)

  • Conditional Jump and Conditional Sets

    • The conditional jump instructions test the following flag bits: sign (S), zero (Z), carry (C), parity (P), and overflow (O) --- see Table 6.1
      • if the condition under test is true, a branch to the label associated with the jump instruction occurs
      • Otherwise, the next sequential step in the program executes
    • The conditional jump instructions all test flag bits, except for the JCXZ (jump if CX=0) and JECXZ (study the example 6.6)
    • See also Table 6.2 for the conditional set instruction


The Jump Group (cont’d)

  • Loop

    • It is a combination of a decrement CX and JNZ conditional jump
    • Example 6.7 shows how to add data in a block of memory with data in another block of memory
  • Conditional Loops

    • LOOPE (loop while equal) jumps if CX <> 0 while an equal condition exists
    • LOOPNE (loop while not equal) jumps if CX <> 0 while a not-equal condition exists


Controlling the Flow of an Assembly Language Program

  • It is much easier to use the assembly language statements .IF., .ELSE., .ELSEIF., and .ENDIF. (study ex. 6.8, 6.9, 6.10 and Table 6.3)

  • DO-WHILE Loops

    • Pair: .WHILE and .ENDW
    • Study example 6.11, 6.12, and 6.13
  • REPEAT-UNTIL Loops

    • Pair: .REPEAT and .UNTIL
    • Study Example 6.14 and 6.15


Procedures

  • A procedure is a group of instructions that usually performs one task

    • reusable - takes small amount of time
    • use stack - can be NEAR or FAR
  • Pair: PROC - ENDP (study example 6.16)

  • CALL

    • It transfers the flow of the program to the procedure
  • CALLs with Register Operands

    • E.g., CALL BX (example 6.17)


Procedures (cont’d)

  • CALLs with Indirect Memory Address

    • useful whenever different subroutines need to be chosen from a program (see Example 6.18)
  • RET

    • It removes either a 16-bit (or 32-bit) number from the stack and places it into IP (and CS)
    • the new location (IP and CS:IP) is the address of the next instruction that immediately follows the most recent CALL to a procedure (Fig. 6.8)
    • Study Example 6.19


Introduction to Interrupt

  • An Interrupt is either a hardware-generated CALL (externally derived from a hardware signal) or a software-generated CALL(internally derived of the execution of an instruction or by some other internal event)

  • Interrupt Vectors

    • An interrupt vector is a 4-byte number stored in the first 1,024 bytes of memory (in the real mode)
    • The vector table is replaced by an interrupt descriptor table that uses 8-byte descriptors to describe each of the interrupts
    • There are 256 different interrupt vectors; each vector contains an address of an interrupt service procedure


Introduction to Interrupt (cont’d)

  • Interrupt Instructions

    • INT, INTO, and INT 3
    • INTs
      • 256 software interrupt (INT) available
      • Whenever a software interrupt executes, it:
        • pushes the flags onto the stack
        • clears the T and I flag bits
        • pushes CS onto the stack
        • fetches the new value for IP/EIP from the vector
        • jump to the new leocation (CS:IP/EIP)


Introduction to Interrupt (cont’d)

    • IRET/IRETD
      • Used only with software or hardware interrupt service procedure
      • The IRET instruction will:
    • INT 3
      • A special software interrupt designed to be used as a breakpoint
      • It is common to insert an INT 3 instruction in software to interrupt or break the flow of the software


Introduction to Interrupt (cont’d)

    • INTO
      • Interrupt on overflow is a conditional software interrupt that tests the overflow flag (O)
        • if O = 0 the INTO instruction performs no operation
        • if O = 1 an INTO instruction executes
      • It appears in software that adds or subtracts signed binary numbers --> INTO detects the overflow condition
    • An Interrupt Service Procedure (Ex. 6.20)
      • The main difference between this procedure and a normal far procedure is that it ends with the IRET instruction instead of the RET instruction, and the contents of the flag register are saved on the stack


Introduction to Interrupt (cont’d)

  • Interrupt Control

    • The set interrupt flag instruction (STI) enables the INTR pin
    • The clear interrupt flag instruction (CLI) disables the INTR pin
  • Interrupts in the Personal Computer

    • See Table 6.5


Machine Control and Miscellanous Instructions

  • These instructions provide control of the carry bit, sample the BUSY/TEST pin, and perform various other functions

  • Controlling the Carry Flag Bit

    • There are three instructions that control the contents of the carry flag: STC (set carry), CLC (clear carry) and CMC (complement carry)
  • WAIT

    • The WAIT instruction monitors the hardware BUSY/TEST pins


Machine Control and Miscellanous Instructions (cont’d)

  • HLT

    • The halt instruction that stops the execution of software
    • Three ways of to exit a halt: by an interrupt, by a hardware reset, or during DMA operation
  • NOP

    • It performs no operation (useful for delaying the operation)




































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