Just-In-Time Java Compilation for the Itanium Processor Tatiana Shpeisman



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Just-In-Time Java Compilation for the Itanium Processor

  • Tatiana Shpeisman

  • Guei-Yuan Lueh

  • Ali-Reza Adl-Tabatabai

  • Intel Labs


Introduction

  • Itanium processor is statically scheduled machine

    • Aggressive compiler techniques to extract ILP
  • Just-In-Time (JIT) compiler must be fast

    • Must consider time & space efficiency of optimizations
    • Balance compilation time with code quality
  • Light-weight compilation techniques

    • Use heuristics for modeling micro architecture
    • Leverage semantics and meta data of JVM


Outline

  • Introduction

  • Compiler overview

  • Register allocation

  • Code scheduling

  • Other optimizations

  • Conclusions



Compiler Structure



Register Allocation

  • Compilation time vs. code quality tradeoff

  • IPF architecture has large register files

    • 128 integer, 128 floating-point, 64 predicate, 8 branch
    • Register Stack Engine (RSE) provides 96 stack registers to each procedure
  • Use linear scan register allocation

    • Linear Scan Register Allocation” by Massimiliano Poletto and Vivek Sarkar


Live Range vs. Live Interval



Coalescing Algorithm

  • Coalesce v and t in v = t iff

    • Live interval of t ends at v = t
    • Live interval of t does not intersect with live range of v
  • Requires one additional reverse pass over IR

    • O(NINST + NVAR * NBB)


Coalescing Speedup



Code Scheduling



Type-based memory disambiguation

  • Use JVM meta data to disambiguate memory locations

    • Type
      • Integer, floating-point, object reference …
    • Kind
      • Object field, array element, virtual table address …
    • Field id
      • putfield #10 vs. putfield #15


Type-Based Disambiguation



Exception Dependencies

  • Java exceptions are precise

  • Naive approach

    • Exception checks end basic blocks
  • Our approach

    • Instruction depends on exception check iff
      • Its destination is live at the exception handler, or
      • It is an exception check for different exception type
      • It is a memory reference that may be guarded by check


Exception Dependency Example



Exception Dependencies



IPF Architecture

  • Execution (functional) unit type – M, I, F, B

  • Instruction (syllable type) – M, A, I, F, B, IL

  • Bundles, templates

    • .mii .mi;;i .mil .mmi .m;;mi .mfi .mmf .mib .mbb .bbb .mmb .mfb
  • Instruction group – no WAR, WAW with some exceptions



Template Selection

  • Pack instructions into bundles

    • Choose slot for each instruction
    • Insert NOP instructions
    • Assign instructions to functional units
  • Problem:

  • Resource over subscription

  • Inaccurate bypass latencies



Algorithm

  • Greedy slot assignment

  • Sort instruction by syllable type

    • M < F < IL < I < A < B


Template Selection Heuristics



Bypass Latency Accuracy



Modeling of Address Computation Latency



Other optimizations

  • Predication

    • Profitability depends on a benchmark
    • Performance variations within 2%
  • Branch hints

    • Up to 50% speedup from using branch hints
  • Sign-extension elimination

    • 1% potential gain for our compiler


Conclusions

  • Light-weight optimizations techniques for Itanium

  • Considering micro architecture is important

  • Language semantics helps to improve ILP

    • Type-based memory disambiguation
    • Exception dependency elimination


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