Inp technology on cmos d. Van Thourhout

InP Technology on CMOS

• D. Van Thourhout

• MWP 2006, Grenoble

Acknowledgements

• The photonics research group at INTEC/IMEC

• P. Dumon, W. Bogaerts, G. Roelkens, J. Van Campenhout, F. Vanlaere, J. Schrauwen, S. Verstuyft, L. Van Landschoot, J. Brouckaert, G. Priem, D. Taillaert, S. Scheerlinck, P. Debackere, S. Selvarajan…
• D. Van Thourhout, P. Bienstman, R. Baets

• The Silicon Process division at IMEC

• Vincent Wiaux, Stephan Beckx, Johan Wouters, Diziana Vangoidsenhoven, Rudi De Ruyter, Johan Mees

• PICMOS partners

• J.M. Fedeli, L. Di Cioccio (LETI) (molecular bonding, processing)
• C. Lagahe, B. Aspar (TRACIT) (planarization)
• C. Seassal, P. Rojo-Romeo, P. Regreny (CNRS-Lyon) (processing, epitaxy)
• R. Notzel, X.J.M. Leijtens (TU/e) (epitaxy)

• European Union, Belgian and Flemish government

Towards CMOS-compatible nanophotonics?

• Outline

• Introduction: why, how, who
• Basic structurs
• Fiber-chip coupling
• Wavelength dependent devices
• Towards active devices: InP on SOI
• Micro-disk lasers
• Fabry-Perot lasers
• Detectors
• Conclusion

Electronics vs. Photonics

• Electronics

• Single material: Silicon (also provides insulator SiO2)
• One platform: CMOS
• Large market: highly tuned, mature processes
• One main building block: the transistor
• Common ITRS roadmap (dominated by a few large companies)
• Size: 10nm  few um

Silicon nanophotonics

• … the solution to all our problems

• Transparent at telecom wavelengths (1.3um, 1.55um)
• High refractive index contrast  ultra-compact circuits
• “Compatible” with CMOS-processing
• Highest quality processes
• High yield, high repeatability

Current Fabrication Process

SOI-nanophotonic wires

• Table updated till Sep. ’05 – Lower values (<2dB) reported but waveguide structure unclear (e.g. Luxtera, EPIC network)

Basic structures

Fiber-chip coupling

Coupling to fiber – Inverse taper

• Inverse taper

• Broad wavelength range
• Single mode
• Easy to fabricate (if you can do the tips)
• Low facet reflections

Coupling to fiber – Grating coupler

• Alternative: Grating couplers

• Waferscale testing
• Waferscale packaging
• High alignment tolerance

Increase effieciency ?

• Standard coupler (33%)

• Improvement: add bottom mirror + apodize

Increase effieciency ?

Complex filters

• 9x16 AWG
• 16 channels, 200GHz channel spacing
• 36 arrayed waveguides
• 0.1mm2 footprint

SOI wavelength router

• 4 x 4 wavelength router

• Four input and four output fibers
• 250 GHz channel spacing
• shallow star couplers, 3μm radius bends
• 3.5dB device insertion loss (waveguides and star coupler), -12 to -14 dB sidelobes

Wavelength dependent devices

SOI-nanowire or Silica-on-Silicon ?

What about actives ?

• SOI-nanophotonics

• Extremely powerful platform for passive guided wave photonics
• We also need actives

• Detectors and modulators

• See next talks

• Sources

• Option 1: use Silicon
• Indirect bandgap material, very inefficient light emitter
• Still: smart scientists manage to squeeze some light out of it (see talk Pavesi)
• Option 2: use III-V materials
• Direct bandgap, efficient light emitter

IST-PICMOS

• GOAL: Build Photonic Interconnect Layer on

• CMOS by waferscale integration

• Solve CMOS interconnect bottleneck
• Use waferscale technologies, compatible with CMOS
• Partners: IMEC, ST, CEA, TRACIT, CNRS-FMNT, NCSR-D, TU/e

III-V on Silicon ???

Proposed integration process

• Starting point: Processed SOI-waveguide wafer

Proposed integration process

• Planarization

Proposed integration process

• Die-to-wafer bonding

Proposed integration process

• Substrate removal

Proposed integration process

• Hardmask deposition

Proposed integration process

• Processing of InP-optoelectronic devices

IST-PICMOS

• Molecular bonding

• InP on SOI-waveguides on CMOS demonstrated (LETI, TRACIT)

Microdisk laser

Lasing characteristics

Temperature dependence

Thermal resistance

Fabry-Perot laser

• Coupling light between III-V and SOI by means of an

• adiabatic inverted taper

• High coupling efficiency (simulated losses below 1dB)
• Large optical bandwidth (>300nm experimentally shown)
• Large fabrication tolerance

Coupling of III-V and SOI

• Inverted taper manufacturable using 248nm deep UV lithography

Fabrication of bonded devices

• Top view and cross section of the fabricated structures

Measurements

Measurements

InGaAs Detectors on SOI

Conclusion

• Silicon-on-insulator technology

• Extremely compact devices
• Fabrication with commercial CMOS technology
• Building blocks demonstrated
• Potential for a “standardised” platform

• WDM-devices

• Basic devices demonstrated (AWG, filters…)

• Extension with active functionality

• Demonstrated electrically contacted micro-disk lasers on Silicon
• Demonstrated Fabry-Perot lasers coupled to SOI-waveguides
• Demonstrated efficient detectors

Acknowledgements

• The photonics research group at INTEC/IMEC

• P. Dumon, W. Bogaerts, G. Roelkens, J. Van Campenhout, F. Vanlaere, J. Schrauwen, S. Verstuyft, L. Van Landschoot, J. Brouckaert, G. Priem, D. Taillaert, S. Scheerlinck, P. Debackere, S. Selvarajan…
• D. Van Thourhout, P. Bienstman, R. Baets

• The Silicon Process division at IMEC

• Vincent Wiaux, Stephan Beckx, Johan Wouters, Diziana Vangoidsenhoven, Rudi De Ruyter, Johan Mees

• PICMOS partners

• J.M. Fedeli, L. Di Cioccio (LETI) (molecular bonding, processing)
• C. Lagahe, B. Aspar (TRACIT) (planarization)
• C. Seassal, P. Rojo-Romeo, P. Regreny (CNRS-Lyon) (processing, epitaxy)
• R. Notzel, X.J.M. Leijtens (TU/e) (epitaxy)

• European Union, Belgian and Flemish government