MASTER THESIS
31 August 2016
DESIGN AND IMPLEMENTATION OF AN FMCW
RADAR SIGNAL PROCESSING MODULE FOR
AUTOMOTIVE APPLICATIONS
Suleyman Suleymanov
Faculty of Electrical Engineering, Mathematics and
Computer Science
Computer Architecture for Embedded Systems
EXAMINATION COMMITTEE
Prof.dr.ir. M.J.G. Bekooij
Prof.dr.ir. G.J.M. Smit
Ir. J.Scholten
V.S. El Hakim, M.Sc.
Abstract
In the recent years, the radar technology, once used predominantly in the
military, has started to emerge in numerous civilian applications. One of the
areas that this technology appeared is the automotive industry. Nowadays,
we can find various radars in modern cars that are used to assist a driver to
ensure a safe drive and increase the quality of the driving experience. The
future of the automotive industry promises to offer a fully autonomous car
which is able to drive itself without any driver assistance. These vehicles will
require powerful radar sensors that can provide precise information about
the surrounding of the vehicle. These sensors will also need a computing
platform that can ensure real-time processing of the received signals.
The subject of this thesis is to investigate the processing platforms for
the real-time signal processing of the automotive FMCW radar developed at
the NXP Semiconductors. The radar sensor is designed to be used in the
self-driving vehicles.
The thesis first investigates the signal processing algorithm for the MIMO
FMCW radar. It is found that the signal processing consists of the three-
dimensional FFT processing. Taking into account the algorithm and the
real-time requirements of the application, the processing capability of the
Starburst MPSoC, 32 core real-time multiprocessor system developed at the
University of Twente, has been evaluated as a base-band processor for the
signal processing. It was found that the multiprocessor system is not capable
to meet the real-time constraints of the application.
As an alternative processing platform, an FPGA implementation of the
algorithm was proposed and implemented in the Virtex-6 FPGA. The imple-
mentations uses pre-built Xilinx IP cores as hardware components to build
the architecture. The architecture also includes a MicroBlaze core which is
used to generate the artificial input data for the algorithm and manage the
operation of hardware components through software.
The results of the implementation show that the architecture can provide
reliable outputs regarding the range, velocity and bearing information. The
accuracy of the results are limited by the range, velocity and angular resolu-
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ABSTRACT
tion which are determined by the specific parameters of the RF front-end and
the designed waveform pattern. However, the real-time performance on the
architecture cannot be achieved due to the high latencies introduced by the
memory transpose operations. A few techniques have been tested to decrease
the latency bottleneck caused by the SDRAM transpose processes, however
none of them have shown any significant improvements.
Contents
Abstract
iii
List of Figures
vii
List of Tables
ix
List of Acronyms
xi
1
Introduction
1
1.1
Context . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
1.2
FMCW Radar Fundamentals
. . . . . . . . . . . . . . . . . .
2
1.3
Research Platform
. . . . . . . . . . . . . . . . . . . . . . . .
5
1.4
Problem Description . . . . . . . . . . . . . . . . . . . . . . .
6
2
FMCW Signal Processing
9
2.1
FMCW Signal Analysis . . . . . . . . . . . . . . . . . . . . . .
9
2.2
MIMO Radar Concept . . . . . . . . . . . . . . . . . . . . . .
15
2.2.1
MIMO Signal Model . . . . . . . . . . . . . . . . . . .
15
3
Requirements
19
3.1
Matlab Model . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
3.2
Computational Analysis . . . . . . . . . . . . . . . . . . . . .
20
3.3
Architecture Considerations . . . . . . . . . . . . . . . . . . .
22
3.4
Signal-flow Analysis . . . . . . . . . . . . . . . . . . . . . . . .
24
4
System Implementation
29
4.1
The algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
4.2
The hardware components . . . . . . . . . . . . . . . . . . . .
31
4.2.1
FFT Core . . . . . . . . . . . . . . . . . . . . . . . . .
31
4.2.2
AXI DMA Core . . . . . . . . . . . . . . . . . . . . . .
32
4.2.3
Memory Interface Core . . . . . . . . . . . . . . . . . .
33
4.2.4
Microblaze Core . . . . . . . . . . . . . . . . . . . . . .
33
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